工作职责：1. Create design block architecture and micro-architecture design specification.
2. RTL design in Verilog, lint, clock domain crossing (CDC) analysis, top level integration, synthesis, timing analysis, timing closure, DFT-related tasks
3. Work with verification team on planning and execution, simulation, debugging block and system level simulations, formal verification, preparation of technical reviews and product/block documentation.
4. Interact with technical leaders of the company and senior staff in engineering, marketing, and corporate development to help ensure successful development of high value technologies and products.
任职资格：1. Bachelor degree or above in microelectronics, electronic information engineering or automation.
2. At least 2 years’ experience in chip related digital circuit design.
3. Familiar with Verilog language, familiar with the transformation from algorithm to RTL.
4. Familiar with Logic Synthesis, Static Timing Analysis.
5. Understand the basic flow of digital APR.